1. Field
This disclosure relates generally to memories, and more specifically, to memories that may benefit from a reduced bitcell power supply voltage during a write operation.
2. Related Art
Some memories, especially static random access memories (SRAMs), may benefit from reducing the bitcell power supply voltage during a write operation. An SRAM cell may have one logic state, due to an imbalance among the transistors in the cell that is particularly difficult to write at the normal bitcell power supply voltage. One of the techniques used to overcome this problem has been to reduce the bitcell power supply during a write operation. Reducing the bitcell power supply voltage at first may appear to provide a power reduction, but the power supply voltage, after the write operation, is restored to the original value for reading. The process of restoring the original voltage requires significant power. Thus, the affect of lowering the bitcell power supply voltage actually results in an increase in power consumption due to the subsequent recharging of the array when the power supply voltage is restored to the original value. Thus, although beneficial for writing, the bitcell power supply reduction approach does have a disadvantage.
Accordingly, there is a continuing need for providing improved techniques relating to reducing the bitcell power supply voltage during the write operation of a memory.